1. Field of the Invention
This disclosure relates to methods of forming a transistor and, more particularly, to methods of forming a transistor having a channel region at a predetermined sidewall of a channel portion hole.
2. Description of the Related Art
In recent years, processing techniques for increasing pattern fidelity in a semiconductor fabrication process with respect to a design drawing has been applied to semiconductor devices in order to pursue high integration and high speed. To this end, the semiconductor devices may include transistors having various structures.
Each of the transistors has a gate pattern, source and drain regions, and a channel region. The gate pattern is disposed on the semiconductor substrate, and the source and drain regions are disposed in the semiconductor substrate to overlap the gate pattern. The channel region is disposed in the semiconductor substrate below the gate pattern to be in contact with the source and drain regions. In addition, the semiconductor substrate along with the gate pattern, the channel region, and the source and drain regions may be connected to electrical terminals.
However, as design rules for the transistor continue to be reduced, the shorter the channel region of the gate pattern must become. To cope with this result, the gate pattern may be changed to have another shape. Accordingly, the transistor further includes channel portion holes in order to increase the effective channel length of the gate pattern. The channel portion hole is a trench that is disposed in the semiconductor substrate. In this case, the channel portion hole is filled with the gate pattern, and the gate pattern increases the effective channel length by using a sidewall of the channel portion hole. At this time, the gate pattern is generally formed to extend upward from a main surface of the semiconductor substrate. When the channel region is formed in the semiconductor substrate by using the gate pattern as a mask, the channel region may not overlap the gate pattern due to a shadow phenomenon of the gate pattern. On the other hand, U.S. Pat. No. 5,016,067 to Kiyoshi Mori, et al. (the '067 patent) discloses a vertical MOS transistor.
According to the '067 patent, the transistor includes a trench, a gate pattern, source and drain regions, and a channel region. The trench is disposed in the semiconductor substrate. The gate pattern is disposed in the trench to conformally fill the trench. The source region, the channel region, and the drain region are vertically disposed in the semiconductor substrate in order to be in contact with a sidewall of the trench.
However, when the transistor has a vertical structure in which the source region, the channel region, and the drain region surround the sidewall of the trench, a width of the channel region may not be limited to the sidewall of the trench. This is the reason that the width of the channel region is determined by diffusion of dopants of the source and drain regions. The diffusion of the dopants of the source and drain regions depends on a semiconductor thermal process applied to the semiconductor substrate. Accordingly, a threshold voltage of the transistor may be partially changed over the whole semiconductor substrate as the size of the semiconductor substrate is increased or as the design rule of the transistor is decreased.
Embodiments of the invention address these and other limitations of the related art.